VSD - Functional Verification Using Embedded-UVM - Part 2

Introduction to object-oriented programming
Udemy
platform
English
language
Other
category
Kunal Ghosh
instructor
VSD - Functional Verification Using Embedded-UVM - Part 2
75
students
1.5 hours
content
Oct 2024
last update
$27.99
regular price

What you will learn

SoC design flow, role of Functional Verification

Logic Modeling, Introduction to Verilog

Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling

Simulation Technology, Discrete Event Simulation

Verification Trends and Challenges

Concepts and Principles of Functional Verification

Testbench Architecture and Components

Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms

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VSD - Functional Verification Using Embedded-UVM - Part 2 – Screenshot 1
Screenshot 1 – VSD - Functional Verification Using Embedded-UVM - Part 2
VSD - Functional Verification Using Embedded-UVM - Part 2 – Screenshot 2
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VSD - Functional Verification Using Embedded-UVM - Part 2 – Screenshot 3
Screenshot 3 – VSD - Functional Verification Using Embedded-UVM - Part 2
VSD - Functional Verification Using Embedded-UVM - Part 2 – Screenshot 4
Screenshot 4 – VSD - Functional Verification Using Embedded-UVM - Part 2

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2706780
udemy ID
15/12/2019
course created date
17/12/2019
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