FPGA Embedded Design, Part 1 - Verilog

Learn FPGA embedded application design starting with the basics and leaving with your own working designs.

4.50 (1102 reviews)

Udemy

platform

English

language

Hardware

What you will learn

Design hardware behavior with the Verilog Hardware Description Language

Simulate Verilog Modules.

The curriculum will take you by the hand through learning Verilog.

In the series, you'll learn how to simulate your designs, how to make them real in an FPGA, and finally how to design and use your own Soft Processor

This first course is about the Verilog Hardware Description Language.

This is NOT a System Verilog course. However, learning Verilog is a starting point if you want to learn System Verilog (Similar to learning C prior to C++).

Course Gallery

FPGA Embedded Design, Part 1 - Verilog – Screenshot 1 — Screenshot 1 – FPGA Embedded Design, Part 1 - Verilog

FPGA Embedded Design, Part 1 - Verilog – Screenshot 2 — Screenshot 2 – FPGA Embedded Design, Part 1 - Verilog

FPGA Embedded Design, Part 1 - Verilog – Screenshot 3 — Screenshot 3 – FPGA Embedded Design, Part 1 - Verilog

FPGA Embedded Design, Part 1 - Verilog – Screenshot 4 — Screenshot 4 – FPGA Embedded Design, Part 1 - Verilog

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Our Verdict

The FPGA Embedded Design, Part 1 - Verilog course on Udemy offers a solid introduction to the Verilog HDL for both beginners and those looking for a refresher. With clear explanations and two coding assignments, it allows learners to gain hands-on experience in a browser-based FPGA design environment. However, there's room for improvement in addressing more advanced topics and offering comprehensive examples to better support the learning journey.

What We Liked

Covers Verilog basics with clear, organized explanations and simulations.
Includes two coding assignments for hands-on experience in a browser-based FPGA design environment.
Designed for learners at various levels, providing additional resources for those seeking deeper understanding.

Potential Drawbacks

Some content may seem too basic or simple for experienced digital designers; could benefit from advanced sections.
Sporadic installations of specific FPGA tools and environments can be time-consuming and hinder learning flow.
Lack of thorough examples before assignments might leave learners uncertain about certain Verilog features.