FPGA Design with VIVADO HLS -High Level Synthesis

Design, Simulate, Synthesize & Export IP with VIVADO HLS : An FPGA Design Approach with C/C++
3.29 (95 reviews)
Udemy
platform
English
language
Hardware
category
Digitronix Nepal
instructor
FPGA Design with VIVADO HLS -High Level Synthesis
625
students
4 hours
content
Mar 2023
last update
$49.99
regular price

What you will learn

Vitis HLS Installation, OpenCV Setup and LAB session

Image Processing with VIVADO HLS & FPGA: Utilizing Computer Vision & Image/Video Processing Libraries on HLS

Sobel Edge Detection IP design in HLS, integrate IP in VIVADO tool and implement it on Zynq FPGA

Designing complete image processing pipeline on VIVADO tool with HLS IP and testing design on Zynq FPGA

Creating C/C++ Project, Simulating, Synthesizing and Exporting it with High Level Synthesis (VIVADO HLS)

Design, Synthesize, Simulate: Counter, Matrix Multiplier, Frequency Modulator ,Numerically Controlled Oscillator and Exporting Design to VIVADO tool

Debugging and Optimizing HLS Project for Resource Utilization on Targeted ZedBoard FPGA

Course Gallery

FPGA Design with VIVADO HLS -High Level Synthesis – Screenshot 1
Screenshot 1 – FPGA Design with VIVADO HLS -High Level Synthesis
FPGA Design with VIVADO HLS -High Level Synthesis – Screenshot 2
Screenshot 2 – FPGA Design with VIVADO HLS -High Level Synthesis
FPGA Design with VIVADO HLS -High Level Synthesis – Screenshot 3
Screenshot 3 – FPGA Design with VIVADO HLS -High Level Synthesis
FPGA Design with VIVADO HLS -High Level Synthesis – Screenshot 4
Screenshot 4 – FPGA Design with VIVADO HLS -High Level Synthesis

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1248160
udemy ID
10/06/2017
course created date
22/11/2019
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