Digital Timing Basics for VLSI Interview & SoC Design

A VLSI Course on Timing Concepts frequently used in Physical Design (Static Timing Analysis - STA), RTL & Circuit Design
4.51 (650 reviews)
Udemy
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English
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Learnin28days Academy
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Digital Timing Basics for VLSI Interview & SoC Design
3 548
students
4 hours
content
Dec 2022
last update
$24.99
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What you will learn

Basics of Flop & Latch Timings

Set-up, Hold, Clock to Q, Clock Skew

Set-up & Hold violation checks

Set-up & Hold violation fixes

Latency Minimization

Set-up & Hold Margin in Digital Ckts

Min & Max Path Analysis

Clock Gating

F-V Curve in SoC

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4204254
udemy ID
25/07/2021
course created date
16/08/2021
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