Scott Dickson
FPGA / ASIC Design Engineer
4.73 (1511 reviews)
4
active courses
0
removed courses
Jul 2020
first content date
Jan 2025
last content date
9288
total students
1511
total reviews
4.73
average rating
24
total content length
Courses
Introduction to VHDL for FPGA and ASIC design
6.5K
students
9.5 hours
content
Aug 2024
updated
$84.99
AXI4 Implementations in FPGA Designs
787
students
8 hours
content
Jan 2025
updated
$74.99
Xilinx Vivado Essentials for the Logic Designer
864
students
2.5 hours
content
Jun 2021
updated
$44.99
Advanced VHDL for Verification
1.2K
students
4.5 hours
content
Jul 2020
updated
$54.99
Related Topics
Vivado
VHDL
